1. Field of the Invention
The invention relates to a semiconductor memory device having an NAND flash memory. More particularly, the invention relates to an erasing method.
2. Description of Related Art
It is well known that an NAND flash memory includes a memory array having an NAND string, and the NAND string has a plurality of memory cells serially connected together. In the memory cells, binary data or multi-bit data may be programmed or erased. Along with device sophistication, the distance between the memory cells and the bit line select transistor or the source line select transistor of the NAND string is reduced, and capacitance coupling between devices or between a device and a substrate is increased, which may render unexpected operational results. For instance, Patent Literature 1 discloses the following: during a data writing operation, a channel voltage of the NAND string is boosted due to coupling effects; in order to prevent the boosted channel voltage of the NAND string from being transmitted to the bit line select transistor, dummy memory cells are placed between the bit line select transistor and the memory cells, and thereby the dummy memory cells may interrupt the connection between the bit line select transistor and the memory cells during the data writing operation.